1. Field
The invention relates to analog-to-digital conversion. In particular, the invention relates to the calibration of analog-to-digital converters (ADC) and programmable precision ADCs.
2. Background
Analog-to-digital converters (ADC) are electrical circuits that convert analog voltages signals to digital voltage signals. Many types of ADCs are made up of numerous data paths consisting of interconnected transistors. Inevitable mismatches between transistors in each of these data paths often hamper performance of the ADC by leading to an offset voltage that can cause errors in the conversion. To reduce this mismatch offset voltage, the total area of the transistors in the data path is often increased, since the threshold voltage (Vt) mismatch for a MOS transistor reduces proportionally to the square root of the gate area of the transistor. As the size of the transistors increases, however, the speed of the ADC is severely degraded. This speed degradation may limit the types of applications the ADC may be used in. Or to compensate the speed degradation, ADC has to consume more power to increase the bandwidth. Thus, what is a needed is a way of reducing the offset voltage in ADCs without having to increase the sizes of the transistors that make up the ADC.